Recent advancement in Microelectronics industries is marked by the unhindered progress of Nanodevices that pledge up gradation of device characteristics offering size miniaturization, high speed, reduced cost and improved power efficiency. Significant contribution to ameliorate device features can be achieved through ground breaking inventions in device geometries, material property improvement and, above all, device downscaling. However, downscaling in nanometer regime results in severe Short Channel Effects (SCEs) that pose severe threats thereby degrading the device performances. Drain-induced barrier lowering (DIBL), Hot carrier effects (HCEs), threshold voltage roll-off, increased Subthreshold swing, etc. are some of the major SCEs that the bulk MOSFET devices are found to encounter when aggressively scaled down in nanometer dimensions. This flagged the way for innovation as well as renovation of the existing MOSFET structures by incorporation of trailblazing technologies like Gate work function engineering, that is, use of more than one material in the gate, use of linearly graded binary metal alloy in the gate, channel engineering such as use of halo doping, graded channel to reduce HCE, strain in the channel to boost carrier mobility and so on. To successfully combat the issue of power leakages, high-k gate stack architectures are quite popular that improves the Subthreshold characteristics of the device. Nowadays, multi-gate MOSFET technologies such as double gate, trigate, gate-all-around MOSFETs with modified geometries have been introduced and are found to perform exceedingly well. With notable advantages starting from enhanced electrostatic control, high field confinement, reduced power consumption to below 50% compared to the planar MOSFET to increased speed by 37%, these pioneering device structures are much appreciated research topics worldwide and are suitably employed to reduce SCEs. Based on these advanced technologies, phenomenal applications of MOSFET have evolved over the years and offered incomparable scientific progress in the current societal scenario. Thus, with apt use of the ingenious technologies coupled with perfection in applications, Nanodevices are predictable Monarchs for reigning the forseeable VLSI Era of Modernization.

Prof. Subir Kumar Sarkar has completed his B. Tech, M. Tech and PhD (Tech) from Institute of Radiophysics and Electronics, University of Calcutta and Post Doctoral from Virginia Commonwealth University (VCU), USA. He has worked around 10 years in industry like Oil and Natural Gas Corporation (ONGC) as Executive Engineer, 26 years in Universities (8 Years in IIEST and 18 Years in Jadavpur University) in different capacities. He was the Head of the Department of Electronics and Telecommunication Engineering, Jadavpur University during 2011-2013, coordinator of the Evening course of M. Tech in “VLSI Design and Microelectronics Technology” 2009 -2013 & 2016- till date and Co-ordinator of IC Design & Fabrication Centre , Jadavpur University from 2016 to till date. He has authored 6 Engineering text books published by CRC Press USA, Artech House USA, PAN STANFOPRD USA, S.Chand & Company Pvt. Ltd., Inda . He has already guided 54 PhD scholars ( 5 more registered and currently working), 21 R&D projects sponsored by different Govt. of India funding agencies have been completed/ongoing, published around 660 technical research papers in archived International/ National journals and peer reviewed conferences. His research Areas include Nanodevices and low power VLSI circuits, Computer networks (MANET & WSN), Digital Watermarking and RFID. He has 13 foreign trips in several countries like USA, France, the United Kingdom, Switzerland, Japan, Thailand, Australia and Bangladesh as Keynote speaker, Special Guest of Honour and Invited speaker for training, presenting papers and visiting sophisticated laboratories as a part of his collaborative research activities. He has delivered around 107 Plenary/Keynote/ Invited talks, 16 IEEE Distinguished Lectures, and chaired 42 technical sessions in various academic programs in India and Abroad. He is a Senior Member of IEEE, IEEE Electron Device Society Distinguished Lecturer, Life fellow of The Institution of Engineers (India) and of Institution of Electronics and Telecommunication Engineers, Life member of ISTE and of Indian Association for the Cultivation of Science (IACS). He has successfully organized two IEEE sponsored International Conferences as Convener (2004) and as General Chair (2012).